System verilog testband for parallel to serial converter
Once it sees the line transition from high to low, it knows that a UART data word is coming. The FPGA is continuously sampling the line. This is how the baud rate gets determined.
#System verilog testband for parallel to serial converter code#
At time 75, after asking for the shift, I got the correct sout but the value in the register should have been 0x14 and not 0x02. The code below uses a generic in VHDL or a parameter in Verilog to determine how many clock cycles there are in each bit. I meant to do a shift right but specified a shift left instead. $time, reset, sin, inbus, mode, value, value, sdata) Psregister r1 (sin, inbus, clk, mode, reset, value, sdata) initial * Do loads for just two of the changes then start a shift at 69 */ # 11 reset = 1 /* Comes out of reset at time 28 */Įnd /* Change the value on the input bus every so often */ Reg sin = 0 /* Make a reset that pulses once. * We need input bus and clock, mode, serial in, and reset as inputs */ Module test /* Make reg inputs and wire outputs for register */ module psregister(pin, clk, load, shift, reset, pout, sout) Test for parallel/serial in-out register modeled on 74194. // Parallel-in, parallel-out, serial out register with synchronous // load & shift and. Note that I have used a 2-bit mode input instead of separate S1 and S0 inputs. I ran it with a slightly modified version of the previous test. It is fairly easy to add these additional functions to our register to get a parallel/serial register.
Wire sin, pin, clk, mode, reset always clk) Module psregister(sin, pin, clk, mode, reset, pout, sout) parameter WIDTH = 8 output pout reset : asynchronous reset to zero (active low) mode : mode control 0 hold, 1 shl, 2 shr, 3 load ė4194 universal shift register but extended to arbitrary number
load & shift and asynchronous clear (reset). Parallel-in, parallel-out, serial out register with synchronous